1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a technique of arranging dummy patterns for metal CMP (Chemical Mechanical Polishing).
2. Description of the Background Art
With refinement of patterns of semiconductor devices, a metal CMP technique has been used as a technique of planarizing interlayer insulating films in multilayer interconnections (the first background art: xe2x80x9cThe State of The Art and Trend of Metal CMPxe2x80x9d, Applied Physics Vol. 68, No. 11, 1999, pp. 1243-1246).
Further, according to the second background art (Japanese Patent Application Laid Open Gazette No. 09-306996), the third background art (Japanese Patent Application Laid Open Gazette No. 10-256255) and the fourth background art (Japanese Patent Application Laid Open Gazette No. 2000-338646), since use of the metal CMP in a case where patterns have large difference in density is likely to cause excessive polishing in a portion of small pattern density (less dense portion), it is proposed that dummy patterns should be provided in a portion of small pattern density besides normal patterns which are originally needed so as to avoid the excessive polishing in the less dense portion for prevention of pattern removal and achieve a further planarization of interlayer insulating films. A process of forming such dummy patterns depends on design rules in layout design of wiring pattern and the amount of data in formation of mask pattern.
Furthermore, the fifth background art (Japanese Patent Application Laid Open Gazette No. 2000-007107) proposes to form dummy patterns besides normal patterns for prevention of excessive erosion caused by use of the metal CMP.
When a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a relatively long gate length (e.g., about 10 xcexcm) is formed on a semiconductor substrate, the pattern density in a MOSFET formation region becomes small. If the metal CMP is performed in a process of manufacturing such a semiconductor device, the metal CMP causes an excessive erosion in the MOSFET formation region and as a result, there is a possibility that a desired planeness may not be obtained. That raises necessity of arranging metal dummy patterns for the metal CMP above a gate electrode of the MOSFET having a relatively long gate length.
The sixth background art (Proc. IEEE 1997 Int. Conference on Microelectronic Test Structure, Vol. 11, March 1997), however, reports that covering an upper layer of a MOS-structure transistor with a metal layer may cause deterioration in characteristics of transistors, such as deterioration in drain currents.
Therefore, formation of dummy patterns above a gate electrode causes a problem that characteristics of a plurality of MOS-structure transistors can not become uniform.
Such a problem arises not only in the MOS-structure transistors having a relatively long gate length but also in other elements. Specifically arises the problem of deterioration in characteristics of elements also when metal dummy patterns are provided above a plurality of resistive elements and metal dummy patterns are provided below an inductor.
The present invention is directed to a semiconductor device. According to a first aspect of the present invention, the semiconductor device comprises: a semiconductor substrate; a MOS-structure transistor formed on a main surface of the semiconductor substrate, comprising a first main electrode region, a second main electrode region and a gate electrode for controlling currents flowing between the first main electrode region and the second main electrode region; an interlayer insulating film formed on an upper surface of the gate electrode, covering the MOS-structure transistor; and a metal dummy pattern formed on an upper surface of the interlayer insulating film and positioned above the upper surface of the gate electrode, and in the semiconductor device of the first aspect, the first main electrode region is opposed to the second main electrode region in a first direction which corresponds to a direction of gate length of the gate electrode, the first main electrode region, the second main electrode region, the gate electrode and the metal dummy pattern extend in a second direction perpendicular to the first direction, which corresponds to a direction of gate width of the gate electrode, and a geometric center of the gate electrode in the second direction coincides with a geometric center of the metal dummy pattern in the second direction.
According to a second aspect of the present invention, in the semiconductor device of the first aspect, the interlayer insulating film and the metal dummy pattern are defined as a first interlayer insulating film and a first-layer metal dummy pattern, respectively, and the semiconductor device of the second aspect further comprises: a second interlayer insulating film covering the first interlayer insulating film and the first-layer metal dummy pattern; and a plurality of second-layer metal dummy patterns formed on portions of an upper surface of the second interlayer insulating film other than a portion above the first-layer metal dummy pattern and arranged in stripes at first intervals in the first direction, and in the semiconductor device of the second aspect, each of the plurality of second-layer metal dummy patterns extends in the second direction, the first-layer metal dummy pattern and the plurality of second-layer metal dummy patterns are arranged at a second interval in a third direction perpendicular to the first direction and the second direction, and a width of each of the plurality of second-layer metal dummy patterns in the first direction is equal to that of the first-layer metal dummy pattern in the first direction.
According to a third aspect of the present invention, the semiconductor device of the second aspect further comprises: a third interlayer insulating film covering the second interlayer insulating film and the plurality of second-layer metal dummy patterns; and a plurality of third-layer metal dummy patterns formed on portions of an upper surface of the third interlayer insulating film other than portions above the plurality of second-layer metal dummy patterns and arranged in stripes at the first intervals in the first direction, and in the semiconductor device of the third aspect, each of the plurality of third-layer metal dummy patterns extends in the second direction, one of the plurality of third-layer metal dummy patterns is positioned above the first-layer metal dummy pattern, a width of each of the plurality of third-layer metal dummy patterns in the first direction is equal to that of the first-layer metal dummy pattern in the first direction, and an interval between the plurality of second-layer metal dummy patterns and the plurality of third-layer metal dummy patterns in the third direction is equal to the second interval.
According to a fourth aspect of the present invention, the semiconductor device of the third aspect further comprises: a fourth interlayer insulating film covering the third interlayer insulating film and the plurality of third-layer metal dummy patterns; and a plurality of fourth-layer metal dummy patterns formed on portions of an upper surface of the fourth interlayer insulating film other than portions above the plurality of third-layer metal dummy patterns and arranged in stripes at the first intervals in the first direction, and in the semiconductor device of the fourth aspect, each of the plurality of fourth-layer metal dummy patterns extends in the second direction, each of the plurality of fourth-layer metal dummy patterns is positioned above a corresponding one out of the plurality of second-layer metal dummy patterns, a width of each of the plurality of fourth-layer metal dummy patterns in the first direction is equal to that of the first-layer metal dummy pattern in the first direction, and an interval between the plurality of third-layer metal dummy patterns and the plurality of fourth-layer metal dummy patterns in the third direction is equal to the second interval.
According to a fifth aspect of the present invention, in the semiconductor device of the first aspect, the first main electrode region and the second main electrode region correspond to a source and a drain, respectively, the metal dummy pattern is electrically connected to the source, and a potential of the source is fixed at a predetermined value.
According to a sixth aspect of the present invention, in the semiconductor device of the first aspect, the first main electrode region and the second main electrode region correspond to a source and a drain, respectively, and the metal dummy pattern is electrically connected to the drain.
According to a seventh aspect of the present invention, the semiconductor device comprises: a semiconductor substrate; an insulating film formed on a main surface of the semiconductor substrate; and a plurality of resistive elements formed on an upper surface of the insulating film and arranged in a first direction, and in the semiconductor device of the seventh aspect, each of the plurality of resistive elements extends in a second direction perpendicular to the first direction, which corresponds to a direction of current flow in the each of resistive elements, and the semiconductor device of the seventh aspect further comprises: an interlayer insulating film covering the insulating film and the plurality of resistive elements; and a plurality of metal dummy patterns formed on an upper surface of the interlayer insulating film and arranged in stripes at first intervals in the second direction, and in the semiconductor device of the seventh aspect, each of the plurality of metal dummy patterns extends in the first direction.
According to an eighth aspect of the present invention, in the semiconductor device of the seventh aspect, the interlayer insulating film and the plurality of metal dummy patterns are defined as a first interlayer insulating film and a plurality of first-layer metal dummy patterns, respectively, and the semiconductor device of the eighth aspect further comprises: a second interlayer insulating film formed on an upper surface of the first interlayer insulating film, covering the first interlayer insulating film and the plurality of first-layer metal dummy patterns; and a plurality of second-layer metal dummy patterns formed on portions of an upper surface of the second interlayer insulating film other than the portions above the plurality of first-layer metal dummy patterns and arranged in stripes at the first intervals in the second direction, and in the semiconductor device of the eighth aspect, each of the plurality of second-layer metal dummy patterns extends in the first direction, the plurality of first-layer metal dummy patterns and the plurality of second-layer metal dummy patterns are arranged at a second interval in a third direction perpendicular to the first direction and the second direction, and a width of each of the plurality of second-layer metal dummy patterns in the second direction is equal to that of each of the plurality of first-layer metal dummy patterns in the second direction.
According to a ninth aspect of the present invention, the semiconductor device of the eighth aspect further comprises: a third interlayer insulating film formed on an upper surface of the second interlayer insulating film, covering the second interlayer insulating film and the plurality of second-layer metal dummy patterns; and a plurality of third-layer metal dummy patterns formed on portions of an upper surface of the third interlayer insulating film other than the portions above the plurality of second-layer metal dummy patterns and arranged in stripes at the first intervals in the second direction, and in the semiconductor device of the ninth aspect, each of the plurality of third-layer metal dummy patterns extends in the first direction, a geometric center of each of the plurality of third-layer metal dummy patterns in the first direction coincides with that of a corresponding one of the plurality of first-layer metal dummy patterns in the first direction, the plurality of second-layer metal dummy patterns and the plurality of third-layer metal dummy patterns are arranged at the second interval in the third direction, and a width of each of the plurality of third-layer metal dummy patterns in the second direction is equal to that of each of the plurality of first-layer metal dummy patterns in the second direction.
According to a tenth aspect of the present invention, the semiconductor device of the ninth aspect further comprises: a fourth interlayer insulating film formed on an upper surface of the third interlayer insulating film, covering the third interlayer insulating film and the plurality of third-layer metal dummy patterns; and a plurality of fourth-layer metal dummy patterns formed on portions of an upper surface of the fourth interlayer insulating film other than the portions above the plurality of third-layer metal dummy patterns and arranged in stripes at the first intervals in the second direction, and in the semiconductor device of the tenth aspect, each of the plurality of fourth-layer metal dummy patterns extends in the first direction, a geometric center of each of the plurality of fourth-layer metal dummy patterns in the first direction coincides with that of a corresponding one of the plurality of second-layer metal dummy patterns in the first direction, the plurality of third-layer metal dummy patterns and the plurality of fourth-layer metal dummy patterns are arranged at the second interval in the third direction, and a width of each of the plurality of fourth-layer metal dummy patterns in the second direction is equal to that of each of the plurality of first-layer metal dummy patterns in the second direction.
According to an eleventh aspect of the present invention, the semiconductor device comprises: a semiconductor substrate; a lower interconnection layer formed on an upper surface of the semiconductor substrate; an upper interconnection layer formed on an upper surface of the lower interconnection layer; an inductor formed in the upper interconnection layer, having a central portion which is an empty region; and a metal dummy pattern formed only in a portion of the lower interconnection layer positioned immediately below the empty region of the inductor.
According to a twelfth aspect of the present invention, the semiconductor device of the eleventh aspect further comprises: a metal guard ring formed in an outer peripheral region of the inductor inside the upper interconnection layer.
According to a thirteenth aspect of the present invention, in the semiconductor device of the twelfth aspect, the metal guard ring is grounded.
The semiconductor device of the first aspect of the present invention can produce an effect of uniformizing the deterioration in characteristics of the MOS-structure transistors caused by the metal dummy pattern while maintaining the essential effect (planarization) of the metal CMP.
The semiconductor device of the second aspect of the present invention can produce an effect of uniformizing the deterioration in characteristics of the MOS-structure transistors caused by a plurality of second-layer metal dummy patterns even when the second-layer metal dummy patterns are provided.
The semiconductor device of the third aspect of the present invention can produce an effect of uniformizing the deterioration in characteristics of the MOS-structure transistors caused by a plurality of third-layer metal dummy patterns even when the third-layer metal dummy patterns are provided.
The semiconductor device of the fourth aspect of the present invention can produce an effect of uniformizing the deterioration in characteristics of the MOS-structure transistors caused by a plurality of fourth-layer metal dummy patterns even when the fourth-layer metal dummy patterns are provided.
The semiconductor device of the fifth aspect of the present invention can produce an effect of improving noise immunity by shielding the gate electrode with the metal pattern.
The semiconductor device of the sixth aspect of the present invention can produce an effect of reducing the deterioration in drain currents caused by providing the metal dummy pattern.
The semiconductor device of the seventh aspect of the present invention can produce an effect of uniformizing the deterioration in characteristics of the resistive elements caused by a plurality of metal dummy patterns while maintaining the essential effect (planarization) of the metal CMP.
The semiconductor device of the eighth aspect of the present invention can produce an effect of uniformizing the deterioration in characteristics of the resistive elements caused by a plurality of second-layer metal dummy patterns even when the second-layer metal dummy patterns are provided.
The semiconductor device of the ninth aspect of the present invention can produce an effect of uniformizing the deterioration in characteristics of the resistive elements caused by a plurality of third-layer metal dummy patterns even when the third-layer metal dummy patterns are provided.
The semiconductor device of the tenth aspect of the present invention can produce an effect of uniformizing the deterioration in characteristics of the resistive elements caused by a plurality of fourth-layer metal dummy patterns even when the fourth-layer metal dummy patterns are provided.
The semiconductor device of the eleventh aspect of the present invention can produce an effect of preventing effectively the deterioration in characteristics of the inductor from being caused by the presence of parasitic capacitance.
The semiconductor device of the twelfth aspect of the present invention can produce an effect of preventing effectively the deterioration in characteristics of the elements outside the inductor and preventing effectively the deterioration in planeness obtained by the CMP.
The semiconductor device of the thirteenth aspect of the present invention can produce an effect of electrically shielding the inductor.
An object of the present invention is to provide a structure of metal dummy patterns which can suppress nonuniformity in characteristics of a plurality of elements as much as possible while maintaining the essential effect of the metal CMP (planeness).